A case for biased programming in flash

The voltage level of flash cells is directly correlated with the wear they experience. Previous studies showed that increasing the ratio of ones to zeroes within a flash page can reduce the amount of bit errors in this page as well as the long-term wear of its cells. Biased programming ensures more ones are programmed than zeroes by employing specialized codes which, in turn, incur non-negligible storage overhead. We propose a novel approach to utilize the page spare area for biased programming, introducing a new tradeoff: while using the spare area for a stronger ECC can correct more errors, biased programming can reduce the number of those errors. We show that as long as the bit error rate is below a pre-determined threshold, biased programming can be applied without compromising the data's durability. When the threshold is reached, we revert to normal programming, but we can use the chip for as much as 24% additional writes, thanks to its reduced wear. We demonstrate the applicability of our approach on real MLC chips. We also perform an initial evaluation on a TLC chip, which exposes the challenges in applying any type of biased programming to TLC flash.