Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

Noa Aflalo; Eilam Yalon; Shahar Kvatinsky

doi:10.1109/VLSID60093.2024.00103

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

Noa Aflalo, Eilam Yalon, Shahar Kvatinsky

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, facilitates the concurrent activation of two or more rows, enabling bitwise operations such as OR, AND, XOR, and NOT on the activated rows. We implement Pinatubo using phase change memory (PCM) and compare our experimental results with the simulated data from the original Pinatubo study. Our findings highlight a significant four-orders of magnitude difference between resistance states, suggesting the robustness of the Pinatubo architecture with PCM technology.

Original language	English
Title of host publication	Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024
Pages	583-586
Number of pages	4
ISBN (Electronic)	9798350384406
DOIs	https://doi.org/10.1109/VLSID60093.2024.00103
State	Published - 2024
Event	37th International Conference on VLSI Design, VLSID 2024 - Kolkata, West Bengal, India Duration: 6 Jan 2024 → 10 Jan 2024

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Conference

Conference	37th International Conference on VLSI Design, VLSID 2024
Country/Territory	India
City	Kolkata, West Bengal
Period	6/01/24 → 10/01/24

Keywords

Arithmetic Logic Unit (ALU)
Central Processing Unit (CPU)
non-stateful logic
non-volatile memories (NVMs)
Phase change memory (PCM)
Pinatubo
processing-in-memory (PIM)
sense amplifier (SA)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSID60093.2024.00103

Cite this

Aflalo, N., Yalon, E., & Kvatinsky, S. (2024). Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. In Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024 (pp. 583-586). (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID60093.2024.00103

Aflalo, Noa ; Yalon, Eilam ; Kvatinsky, Shahar. / Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. 2024. pp. 583-586 (Proceedings of the IEEE International Conference on VLSI Design).

@inproceedings{eefe681b7034427c95f97b9185ab531c,

title = "Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture",

abstract = "This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, facilitates the concurrent activation of two or more rows, enabling bitwise operations such as OR, AND, XOR, and NOT on the activated rows. We implement Pinatubo using phase change memory (PCM) and compare our experimental results with the simulated data from the original Pinatubo study. Our findings highlight a significant four-orders of magnitude difference between resistance states, suggesting the robustness of the Pinatubo architecture with PCM technology.",

keywords = "Arithmetic Logic Unit (ALU), Central Processing Unit (CPU), non-stateful logic, non-volatile memories (NVMs), Phase change memory (PCM), Pinatubo, processing-in-memory (PIM), sense amplifier (SA)",

author = "Noa Aflalo and Eilam Yalon and Shahar Kvatinsky",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 37th International Conference on VLSI Design, VLSID 2024 ; Conference date: 06-01-2024 Through 10-01-2024",

year = "2024",

doi = "10.1109/VLSID60093.2024.00103",

language = "אנגלית",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "583--586",

booktitle = "Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024",

}

Aflalo, N, Yalon, E & Kvatinsky, S 2024, Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. in Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. Proceedings of the IEEE International Conference on VLSI Design, pp. 583-586, 37th International Conference on VLSI Design, VLSID 2024, Kolkata, West Bengal, India, 6/01/24. https://doi.org/10.1109/VLSID60093.2024.00103

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. / Aflalo, Noa; Yalon, Eilam ; Kvatinsky, Shahar.
Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. 2024. p. 583-586 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

AU - Aflalo, Noa

AU - Yalon, Eilam

AU - Kvatinsky, Shahar

PY - 2024

Y1 - 2024

N2 - This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, facilitates the concurrent activation of two or more rows, enabling bitwise operations such as OR, AND, XOR, and NOT on the activated rows. We implement Pinatubo using phase change memory (PCM) and compare our experimental results with the simulated data from the original Pinatubo study. Our findings highlight a significant four-orders of magnitude difference between resistance states, suggesting the robustness of the Pinatubo architecture with PCM technology.

AB - This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, facilitates the concurrent activation of two or more rows, enabling bitwise operations such as OR, AND, XOR, and NOT on the activated rows. We implement Pinatubo using phase change memory (PCM) and compare our experimental results with the simulated data from the original Pinatubo study. Our findings highlight a significant four-orders of magnitude difference between resistance states, suggesting the robustness of the Pinatubo architecture with PCM technology.

KW - Arithmetic Logic Unit (ALU)

KW - Central Processing Unit (CPU)

KW - non-stateful logic

KW - non-volatile memories (NVMs)

KW - Phase change memory (PCM)

KW - Pinatubo

KW - processing-in-memory (PIM)

KW - sense amplifier (SA)

UR - http://www.scopus.com/inward/record.url?scp=85190385098&partnerID=8YFLogxK

U2 - 10.1109/VLSID60093.2024.00103

DO - 10.1109/VLSID60093.2024.00103

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85190385098

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 583

EP - 586

BT - Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024

T2 - 37th International Conference on VLSI Design, VLSID 2024

Y2 - 6 January 2024 through 10 January 2024

ER -

Aflalo N, Yalon E , Kvatinsky S. Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. In Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. 2024. p. 583-586. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID60093.2024.00103

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture

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