Characterization and Architecture of Monolithic NP-CMOS-SiPM Array for ToF Measurements

This article focuses on the characterization and architecture of a new mixed design approach to monolithic CMOS-silicon-photomultiplier (SiPM), where the mixed-signal circuitry as well as the logical concepts are implemented at the die level. The new architecture contains two key areas: 1) a method for sampling, filtering, and converting the electrical signal generated by the SiPM to the digital domain by taking advantage of the nature of the SiPM as an 'optical-to-digital converter' and 2) a fully digital configurable method, which requires just one clock generator, enabling sampling at an adjustable time window (gating method) and reduces background noise. We report the design, simulation, and measurement results. The system was fabricated at a low-cost 0.18∼\mathrm {[{\mu {\mathrm{ m}}}]}0.18 - \mu \text{m} CMOS process yet achieves a clock rate of 1 GHz, high timing and photon counting resolution, and low jitter. The reported demonstrator may be applied to 3-D range measurements, light detection and ranging (LIDAR), time-of-flight (ToF) system, and gaming systems.