Abstract
As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to increasing hop-distances, since long paths involve more routers. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide routes with shorter hop-distances and therefore are more adequate for large systems. The introduction of hierarchical NoCs poses new challenges as they should provide the shortest hop-distance for as many as possible source-destination pairs with minimal interference among packets, at the lowest hardware and system costs. In this paper, a framework for design and dynamic management of hierarchical NoCs is introduced. The design space of hierarchical NoCs is explored under cost and performance constraints. A dynamic management scheme termed DTrD (Dynamic Traffic Distribution) is proposed. DTrD enables to dynamically adapt the routing policy in hierarchical NoCs to varying traffic conditions. Finally, a set of guidelines is formulated for proper design and dynamic control of hierarchical NoCs.
| Original language | English |
|---|---|
| Pages (from-to) | 154-166 |
| Number of pages | 13 |
| Journal | Microprocessors and Microsystems |
| Volume | 40 |
| DOIs | |
| State | Published - 1 Feb 2016 |
Keywords
- Adaptive routing
- Hierarchical networks on chip
- Load balancing
- Low latency design
- Traffic monitoring
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence