Abstract
Wafer Fabrication Plants (FABs) are arranged in a two-dimension (2D) layout, usually in a single floor. These layouts imply various constraints on the work-in-process (WIP) and the material handling systems. In contrast, Automated Storage/Retrieval Systems (AS/RS) arranged in a three-dimension (3D) layout aisle, where each aisle is served by a robotic arm that moves back and forth between the aisle's entrance point and its storage locations. This paper offers an AS/RS-based 3D layout for FABs. First, we formulate the general 3D layout design problem and develop a heuristic algorithm to solve it. Then, we evaluate the proposed layout comparative to its 2D counterpart. Finally, we test the proposed layout by simulating an actual data taken from the semiconductor industry and comparing the performance of 2D and 3D layouts, 30% throughput time reduction observed.
Original language | English |
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Article number | FD81 |
Pages (from-to) | 281-284 |
Number of pages | 4 |
Journal | IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings |
DOIs | |
State | Published - 2005 |
Event | IEEE International Symposium on Semiconductor Manufacturing, Conference Proceedings - San Jose, CA, United States Duration: 13 Sep 2005 → 15 Sep 2005 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- General Engineering
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering