Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696))

Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; AVINOAM KOLODNY

doi:10.1109/TVLSI.2010.2052421

Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696))

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, AVINOAM KOLODNY

Research output: Contribution to journal › Comment/debate

Original language	English
Article number	5499447
Pages (from-to)	1262
Number of pages	1
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	18
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2010.2052421
State	Published - Aug 2010

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2010.2052421

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Morgenshtein, A., Friedman, E. G., Ginosar, R., & KOLODNY, AVINOAM. (2010). Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696)). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(8), 1262. Article 5499447. https://doi.org/10.1109/TVLSI.2010.2052421

Morgenshtein, Arkadiy ; Friedman, Eby G. ; Ginosar, Ran et al. / Erratum : Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696)). In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 ; Vol. 18, No. 8. pp. 1262.

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author = "Arkadiy Morgenshtein and Friedman, {Eby G.} and Ran Ginosar and AVINOAM KOLODNY",

year = "2010",

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Morgenshtein, A, Friedman, EG, Ginosar, R & KOLODNY, AVINOAM 2010, 'Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696))', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 8, 5499447, pp. 1262. https://doi.org/10.1109/TVLSI.2010.2052421

Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696)). / Morgenshtein, Arkadiy; Friedman, Eby G.; Ginosar, Ran et al.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 8, 5499447, 08.2010, p. 1262.

Research output: Contribution to journal › Comment/debate

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Morgenshtein A, Friedman EG, Ginosar R , KOLODNY AVINOAM. Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696)). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 Aug;18(8):1262. 5499447. doi: 10.1109/TVLSI.2010.2052421

Erratum: Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010) 18:5 (689-696))

ASJC Scopus subject areas

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