Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design

Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers used to achieve timing goals through a useful skew clock design methodology. Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential, thus making predictable delays and useful skews highly important. We examine interconnect shielding intradie within-die (WID) and interdie die-to-die (D2D) variations under a wide variety of (P,V,T) corners, and show their applicability and ability to achieve clock design timing goals. The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip supported by a rigorous provable estimation methodology.