A Design Flow and Tool for Avoiding Asymmetric Aging

Advance process nodes may incur severe reliability concerns due to asymmetric aging, which induces unequal timing degradation of logic elements over time. Most existing tools can handle asymmetric aging in relatively small circuitry and rely on a physical design approach. This paper extends asymmetric aging avoidance design flows using automated engineering change order (ECO) flow. The proposed tool and design flow can be simply integrated as part of standard flows of large-scale integrated circuits. Our experimental analysis of various data-path logic structures reveals that the tool can eliminate reliability issues while introducing minor overhead.