Asymmetric aging effect on modern microprocessors

Reliability, a crucial requirement in any modern microprocessor, assures correct execution over its lifetime. As mission critical components are becoming common in commodity systems, e.g., control of autonomous cars, the demand for reliable processing continues to grow. The latest process technologies have aggravated the situation by causing microprocessors to be highly vulnerable to reliability concerns. This paper examines the asymmetric aging phenomenon, which is a major reliability worry in advanced process nodes. In this phenomenon, logical elements and memory cells suffer from unequal timing degradation over their lifetimes and, consequently, raise reliability concerns. Thus far, most studies approached asymmetric aging from a circuit or physical design viewpoint, but these solutions were quite limited and suboptimal. In this paper, we introduce an asymmetric aging-aware microarchitecture that aims to reduce the phenomenon's impact. The study is mainly focused on the following subsystems: execution units, register files and memory hierarchy. Our experiments indicate that the proposed solutions incur minimal overhead while significantly mitigating asymmetric aging stress.