TY - GEN
T1 - Scaling multi-core network processors without the reordering bottleneck
AU - Shpiner, Alexander
AU - Keslassy, Isaac
AU - Cohen, Rami
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/16
Y1 - 2014/9/16
N2 - Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks.
AB - Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks.
UR - http://www.scopus.com/inward/record.url?scp=84908592655&partnerID=8YFLogxK
U2 - 10.1109/HPSR.2014.6900895
DO - 10.1109/HPSR.2014.6900895
M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???
AN - SCOPUS:84908592655
T3 - 2014 IEEE 15th International Conference on High Performance Switching and Routing, HPSR 2014
SP - 146
EP - 153
BT - 2014 IEEE 15th International Conference on High Performance Switching and Routing, HPSR 2014
T2 - 2014 IEEE 15th International Conference on High Performance Switching and Routing, HPSR 2014
Y2 - 1 July 2014 through 4 July 2014
ER -